#ifndef MAC_REG_RX_PCS_H
#define MAC_REG_RX_PCS_H

/* Base address of Module's Register */
#define CSR_RX_PCS_BASE (0x4000)

#define CSR_RX_PCS_INT_STATUS (CSR_RX_PCS_BASE + 0x0)
#define CSR_RX_PCS_INT_ENABLE (CSR_RX_PCS_BASE + 0x4)
#define CSR_RX_PCS_INT_SET (CSR_RX_PCS_BASE + 0x8)
#define CSR_RX_PCS_OVF_INT_STATUS (CSR_RX_PCS_BASE + 0xc)
#define CSR_RX_PCS_OVF_INT_ENABLE (CSR_RX_PCS_BASE + 0x10)
#define CSR_RX_PCS_OVF_INT_SET (CSR_RX_PCS_BASE + 0x14)
#define CSR_RX_PCS_SD_INT_STATUS (CSR_RX_PCS_BASE + 0x18)
#define CSR_RX_PCS_SD_INT_ENABLE (CSR_RX_PCS_BASE + 0x1c)
#define CSR_RX_PCS_SD_INT_SET (CSR_RX_PCS_BASE + 0x20)
#define CSR_RX_PCS_SF_INT_STATUS (CSR_RX_PCS_BASE + 0x24)
#define CSR_RX_PCS_SF_INT_ENABLE (CSR_RX_PCS_BASE + 0x28)
#define CSR_RX_PCS_SF_INT_SET (CSR_RX_PCS_BASE + 0x2c)
#define CSR_RX_PCS_IERR_U_INFO (CSR_RX_PCS_BASE + 0x80)
#define CSR_RX_PCS_IERR_C_INFO (CSR_RX_PCS_BASE + 0x84)
#define CSR_RX_PCS_IERR_U_CNT (CSR_RX_PCS_BASE + 0x88)
#define CSR_RX_PCS_IERR_C_CNT (CSR_RX_PCS_BASE + 0x8c)
#define CSR_RX_PCS_PHY_RSTN (CSR_RX_PCS_BASE + 0xa0)
#define CSR_RX_PCS_DBG_IERR_INSERT (CSR_RX_PCS_BASE + 0xc0)
#define CSR_RX_PCS_DBG_COM_CTRL (CSR_RX_PCS_BASE + 0xc4)
#define CSR_RX_PCS_RSFEC_TDM_DELAY (CSR_RX_PCS_BASE + 0xc8)
#define CSR_RX_PCS_AN_LINK_CTRL (CSR_RX_PCS_BASE + 0xcc)
#define CSR_RX_PCS_LINK_UP_TYPE_CTRL (CSR_RX_PCS_BASE + 0xd0)
#define CSR_RX_PCS_DBG_DEC_CAP (CSR_RX_PCS_BASE + 0xd4)
#define CSR_RX_PCS_DBG_DEC_CAP_CMD (CSR_RX_PCS_BASE + 0xd8)
#define CSR_RX_PCS_DBG_DEC_CAP_STATUS (CSR_RX_PCS_BASE + 0xdc)
#define CSR_RX_PCS_DBG_DEC_CAP_DATA (CSR_RX_PCS_BASE + 0xe0)
#define CSR_RX_PCS_LINK_STATUS (CSR_RX_PCS_BASE + 0xf0)
#define CSR_RX_PCS_LOOP_FIFO_CURR_STATUS (CSR_RX_PCS_BASE + 0xf4)
#define CSR_RX_PCS_LOOP_FIFO_HIS_STATUS (CSR_RX_PCS_BASE + 0xf8)
#define CSR_RX_PCS_SPARE (CSR_RX_PCS_BASE + 0x100)
#define CSR_RX_PCS_SPARE_CNT (CSR_RX_PCS_BASE + 0x104)
#define CSR_RX_PCS_PHY0_CTRL_CFG (CSR_RX_PCS_BASE + 0x400)
#define CSR_RX_PCS_PHY0_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x404)
#define CSR_RX_PCS_PHY0_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x408)
#define CSR_RX_PCS_PHY0_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x40c)
#define CSR_RX_PCS_PHY0_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x410)
#define CSR_RX_PCS_PHY0_TEST_CONTROL (CSR_RX_PCS_BASE + 0x414)
#define CSR_RX_PCS_PHY0_DBG_CONTROL (CSR_RX_PCS_BASE + 0x418)
#define CSR_RX_PCS_PHY0_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x41c)
#define CSR_RX_PCS_PHY0_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x420)
#define CSR_RX_PCS_PHY0_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x424)
#define CSR_RX_PCS_PHY0_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x428)
#define CSR_RX_PCS_PHY0_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x42c)
#define CSR_RX_PCS_PHY0_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x430)
#define CSR_RX_PCS_PHY0_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x434)
#define CSR_RX_PCS_PHY0_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x438)
#define CSR_RX_PCS_PHY0_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x43c)
#define CSR_RX_PCS_PHY0_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x440)
#define CSR_RX_PCS_PHY0_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x444)
#define CSR_RX_PCS_PHY0_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x448)
#define CSR_RX_PCS_PHY0_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x44c)
#define CSR_RX_PCS_PHY0_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x450)
#define CSR_RX_PCS_PHY0_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x454)
#define CSR_RX_PCS_PHY0_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x458)
#define CSR_RX_PCS_PHY0_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x45c)
#define CSR_RX_PCS_PHY0_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x460)
#define CSR_RX_PCS_PHY0_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x464)
#define CSR_RX_PCS_PHY0_BER_CNT (CSR_RX_PCS_BASE + 0x468)
#define CSR_RX_PCS_PHY0_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x46c)
#define CSR_RX_PCS_PHY0_E_BLK_CNT (CSR_RX_PCS_BASE + 0x470)
#define CSR_RX_PCS_PHY0_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x474)
#define CSR_RX_PCS_PHY0_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x478)
#define CSR_RX_PCS_PHY0__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x480)
#define CSR_RX_PCS_PHY0_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x500)
#define CSR_RX_PCS_PHY0_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x504)
#define CSR_RX_PCS_PHY0_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x508)
#define CSR_RX_PCS_PHY0_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x50c)
#define CSR_RX_PCS_PHY0_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x510)
#define CSR_RX_PCS_PHY0_BASER_800G_CONTROL (CSR_RX_PCS_BASE + 0x600)
#define CSR_RX_PCS_PHY0_TEST_800G_PRBS_MODE (CSR_RX_PCS_BASE + 0x604)
#define CSR_RX_PCS_PHY0_PRBS_800G_ERR_CNT (CSR_RX_PCS_BASE + 0x608)
#define CSR_RX_PCS_PHY0_PRBS_800G_BIT_CNT (CSR_RX_PCS_BASE + 0x60c)
#define CSR_RX_PCS_PHY0_PRBS_800G_CW_CNT (CSR_RX_PCS_BASE + 0x610)
#define CSR_RX_PCS_PHY0_INV_BLOCK_800G_CNT (CSR_RX_PCS_BASE + 0x614)
#define CSR_RX_PCS_PHY0_DBG_CUR_800G_STATUS (CSR_RX_PCS_BASE + 0x618)
#define CSR_RX_PCS_PHY0_DBG_HIS_800G_STATUS (CSR_RX_PCS_BASE + 0x61c)
#define CSR_RX_PCS_PHY1_CTRL_CFG (CSR_RX_PCS_BASE + 0x800)
#define CSR_RX_PCS_PHY1_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x804)
#define CSR_RX_PCS_PHY1_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x808)
#define CSR_RX_PCS_PHY1_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x80c)
#define CSR_RX_PCS_PHY1_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x810)
#define CSR_RX_PCS_PHY1_TEST_CONTROL (CSR_RX_PCS_BASE + 0x814)
#define CSR_RX_PCS_PHY1_DBG_CONTROL (CSR_RX_PCS_BASE + 0x818)
#define CSR_RX_PCS_PHY1_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x81c)
#define CSR_RX_PCS_PHY1_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x820)
#define CSR_RX_PCS_PHY1_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x824)
#define CSR_RX_PCS_PHY1_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x828)
#define CSR_RX_PCS_PHY1_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x82c)
#define CSR_RX_PCS_PHY1_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x830)
#define CSR_RX_PCS_PHY1_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x834)
#define CSR_RX_PCS_PHY1_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x838)
#define CSR_RX_PCS_PHY1_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x83c)
#define CSR_RX_PCS_PHY1_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x840)
#define CSR_RX_PCS_PHY1_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x844)
#define CSR_RX_PCS_PHY1_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x848)
#define CSR_RX_PCS_PHY1_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x84c)
#define CSR_RX_PCS_PHY1_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x850)
#define CSR_RX_PCS_PHY1_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x854)
#define CSR_RX_PCS_PHY1_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x858)
#define CSR_RX_PCS_PHY1_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x85c)
#define CSR_RX_PCS_PHY1_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x860)
#define CSR_RX_PCS_PHY1_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x864)
#define CSR_RX_PCS_PHY1_BER_CNT (CSR_RX_PCS_BASE + 0x868)
#define CSR_RX_PCS_PHY1_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x86c)
#define CSR_RX_PCS_PHY1_E_BLK_CNT (CSR_RX_PCS_BASE + 0x870)
#define CSR_RX_PCS_PHY1_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x874)
#define CSR_RX_PCS_PHY1_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x878)
#define CSR_RX_PCS_PHY1__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x880)
#define CSR_RX_PCS_PHY1_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x900)
#define CSR_RX_PCS_PHY1_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x904)
#define CSR_RX_PCS_PHY1_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x908)
#define CSR_RX_PCS_PHY1_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x90c)
#define CSR_RX_PCS_PHY1_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x910)
#define CSR_RX_PCS_PHY2_CTRL_CFG (CSR_RX_PCS_BASE + 0xa00)
#define CSR_RX_PCS_PHY2_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0xa04)
#define CSR_RX_PCS_PHY2_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0xa08)
#define CSR_RX_PCS_PHY2_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0xa0c)
#define CSR_RX_PCS_PHY2_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0xa10)
#define CSR_RX_PCS_PHY2_TEST_CONTROL (CSR_RX_PCS_BASE + 0xa14)
#define CSR_RX_PCS_PHY2_DBG_CONTROL (CSR_RX_PCS_BASE + 0xa18)
#define CSR_RX_PCS_PHY2_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0xa1c)
#define CSR_RX_PCS_PHY2_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xa20)
#define CSR_RX_PCS_PHY2_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xa24)
#define CSR_RX_PCS_PHY2_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xa28)
#define CSR_RX_PCS_PHY2_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xa2c)
#define CSR_RX_PCS_PHY2_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xa30)
#define CSR_RX_PCS_PHY2_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xa34)
#define CSR_RX_PCS_PHY2_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xa38)
#define CSR_RX_PCS_PHY2_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xa3c)
#define CSR_RX_PCS_PHY2_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa40)
#define CSR_RX_PCS_PHY2_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa44)
#define CSR_RX_PCS_PHY2_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa48)
#define CSR_RX_PCS_PHY2_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xa4c)
#define CSR_RX_PCS_PHY2_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa50)
#define CSR_RX_PCS_PHY2_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa54)
#define CSR_RX_PCS_PHY2_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa58)
#define CSR_RX_PCS_PHY2_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xa5c)
#define CSR_RX_PCS_PHY2_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0xa60)
#define CSR_RX_PCS_PHY2_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0xa64)
#define CSR_RX_PCS_PHY2_BER_CNT (CSR_RX_PCS_BASE + 0xa68)
#define CSR_RX_PCS_PHY2_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0xa6c)
#define CSR_RX_PCS_PHY2_E_BLK_CNT (CSR_RX_PCS_BASE + 0xa70)
#define CSR_RX_PCS_PHY2_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0xa74)
#define CSR_RX_PCS_PHY2_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0xa78)
#define CSR_RX_PCS_PHY2__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0xa80)
#define CSR_RX_PCS_PHY2_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0xb00)
#define CSR_RX_PCS_PHY2_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0xb04)
#define CSR_RX_PCS_PHY2_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0xb08)
#define CSR_RX_PCS_PHY2_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0xb0c)
#define CSR_RX_PCS_PHY2_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0xb10)
#define CSR_RX_PCS_PHY3_CTRL_CFG (CSR_RX_PCS_BASE + 0xc00)
#define CSR_RX_PCS_PHY3_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0xc04)
#define CSR_RX_PCS_PHY3_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0xc08)
#define CSR_RX_PCS_PHY3_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0xc0c)
#define CSR_RX_PCS_PHY3_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0xc10)
#define CSR_RX_PCS_PHY3_TEST_CONTROL (CSR_RX_PCS_BASE + 0xc14)
#define CSR_RX_PCS_PHY3_DBG_CONTROL (CSR_RX_PCS_BASE + 0xc18)
#define CSR_RX_PCS_PHY3_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0xc1c)
#define CSR_RX_PCS_PHY3_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xc20)
#define CSR_RX_PCS_PHY3_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xc24)
#define CSR_RX_PCS_PHY3_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xc28)
#define CSR_RX_PCS_PHY3_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xc2c)
#define CSR_RX_PCS_PHY3_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xc30)
#define CSR_RX_PCS_PHY3_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xc34)
#define CSR_RX_PCS_PHY3_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xc38)
#define CSR_RX_PCS_PHY3_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xc3c)
#define CSR_RX_PCS_PHY3_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc40)
#define CSR_RX_PCS_PHY3_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc44)
#define CSR_RX_PCS_PHY3_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc48)
#define CSR_RX_PCS_PHY3_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xc4c)
#define CSR_RX_PCS_PHY3_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc50)
#define CSR_RX_PCS_PHY3_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc54)
#define CSR_RX_PCS_PHY3_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc58)
#define CSR_RX_PCS_PHY3_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xc5c)
#define CSR_RX_PCS_PHY3_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0xc60)
#define CSR_RX_PCS_PHY3_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0xc64)
#define CSR_RX_PCS_PHY3_BER_CNT (CSR_RX_PCS_BASE + 0xc68)
#define CSR_RX_PCS_PHY3_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0xc6c)
#define CSR_RX_PCS_PHY3_E_BLK_CNT (CSR_RX_PCS_BASE + 0xc70)
#define CSR_RX_PCS_PHY3_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0xc74)
#define CSR_RX_PCS_PHY3_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0xc78)
#define CSR_RX_PCS_PHY3__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0xc80)
#define CSR_RX_PCS_PHY3_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0xd00)
#define CSR_RX_PCS_PHY3_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0xd04)
#define CSR_RX_PCS_PHY3_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0xd08)
#define CSR_RX_PCS_PHY3_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0xd0c)
#define CSR_RX_PCS_PHY3_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0xd10)
#define CSR_RX_PCS_PHY4_CTRL_CFG (CSR_RX_PCS_BASE + 0xe00)
#define CSR_RX_PCS_PHY4_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0xe04)
#define CSR_RX_PCS_PHY4_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0xe08)
#define CSR_RX_PCS_PHY4_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0xe0c)
#define CSR_RX_PCS_PHY4_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0xe10)
#define CSR_RX_PCS_PHY4_TEST_CONTROL (CSR_RX_PCS_BASE + 0xe14)
#define CSR_RX_PCS_PHY4_DBG_CONTROL (CSR_RX_PCS_BASE + 0xe18)
#define CSR_RX_PCS_PHY4_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0xe1c)
#define CSR_RX_PCS_PHY4_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xe20)
#define CSR_RX_PCS_PHY4_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xe24)
#define CSR_RX_PCS_PHY4_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0xe28)
#define CSR_RX_PCS_PHY4_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0xe2c)
#define CSR_RX_PCS_PHY4_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xe30)
#define CSR_RX_PCS_PHY4_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xe34)
#define CSR_RX_PCS_PHY4_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0xe38)
#define CSR_RX_PCS_PHY4_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0xe3c)
#define CSR_RX_PCS_PHY4_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe40)
#define CSR_RX_PCS_PHY4_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe44)
#define CSR_RX_PCS_PHY4_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe48)
#define CSR_RX_PCS_PHY4_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0xe4c)
#define CSR_RX_PCS_PHY4_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe50)
#define CSR_RX_PCS_PHY4_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe54)
#define CSR_RX_PCS_PHY4_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe58)
#define CSR_RX_PCS_PHY4_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0xe5c)
#define CSR_RX_PCS_PHY4_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0xe60)
#define CSR_RX_PCS_PHY4_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0xe64)
#define CSR_RX_PCS_PHY4_BER_CNT (CSR_RX_PCS_BASE + 0xe68)
#define CSR_RX_PCS_PHY4_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0xe6c)
#define CSR_RX_PCS_PHY4_E_BLK_CNT (CSR_RX_PCS_BASE + 0xe70)
#define CSR_RX_PCS_PHY4_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0xe74)
#define CSR_RX_PCS_PHY4_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0xe78)
#define CSR_RX_PCS_PHY4__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0xe80)
#define CSR_RX_PCS_PHY4_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0xf00)
#define CSR_RX_PCS_PHY4_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0xf04)
#define CSR_RX_PCS_PHY4_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0xf08)
#define CSR_RX_PCS_PHY4_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0xf0c)
#define CSR_RX_PCS_PHY4_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0xf10)
#define CSR_RX_PCS_PHY5_CTRL_CFG (CSR_RX_PCS_BASE + 0x1000)
#define CSR_RX_PCS_PHY5_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x1004)
#define CSR_RX_PCS_PHY5_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x1008)
#define CSR_RX_PCS_PHY5_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x100c)
#define CSR_RX_PCS_PHY5_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x1010)
#define CSR_RX_PCS_PHY5_TEST_CONTROL (CSR_RX_PCS_BASE + 0x1014)
#define CSR_RX_PCS_PHY5_DBG_CONTROL (CSR_RX_PCS_BASE + 0x1018)
#define CSR_RX_PCS_PHY5_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x101c)
#define CSR_RX_PCS_PHY5_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1020)
#define CSR_RX_PCS_PHY5_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x1024)
#define CSR_RX_PCS_PHY5_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1028)
#define CSR_RX_PCS_PHY5_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x102c)
#define CSR_RX_PCS_PHY5_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1030)
#define CSR_RX_PCS_PHY5_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x1034)
#define CSR_RX_PCS_PHY5_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1038)
#define CSR_RX_PCS_PHY5_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x103c)
#define CSR_RX_PCS_PHY5_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1040)
#define CSR_RX_PCS_PHY5_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1044)
#define CSR_RX_PCS_PHY5_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1048)
#define CSR_RX_PCS_PHY5_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x104c)
#define CSR_RX_PCS_PHY5_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1050)
#define CSR_RX_PCS_PHY5_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1054)
#define CSR_RX_PCS_PHY5_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1058)
#define CSR_RX_PCS_PHY5_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x105c)
#define CSR_RX_PCS_PHY5_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x1060)
#define CSR_RX_PCS_PHY5_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x1064)
#define CSR_RX_PCS_PHY5_BER_CNT (CSR_RX_PCS_BASE + 0x1068)
#define CSR_RX_PCS_PHY5_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x106c)
#define CSR_RX_PCS_PHY5_E_BLK_CNT (CSR_RX_PCS_BASE + 0x1070)
#define CSR_RX_PCS_PHY5_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x1074)
#define CSR_RX_PCS_PHY5_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x1078)
#define CSR_RX_PCS_PHY5__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x1080)
#define CSR_RX_PCS_PHY5_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x1100)
#define CSR_RX_PCS_PHY5_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x1104)
#define CSR_RX_PCS_PHY5_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x1108)
#define CSR_RX_PCS_PHY5_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x110c)
#define CSR_RX_PCS_PHY5_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x1110)
#define CSR_RX_PCS_PHY6_CTRL_CFG (CSR_RX_PCS_BASE + 0x1200)
#define CSR_RX_PCS_PHY6_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x1204)
#define CSR_RX_PCS_PHY6_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x1208)
#define CSR_RX_PCS_PHY6_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x120c)
#define CSR_RX_PCS_PHY6_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x1210)
#define CSR_RX_PCS_PHY6_TEST_CONTROL (CSR_RX_PCS_BASE + 0x1214)
#define CSR_RX_PCS_PHY6_DBG_CONTROL (CSR_RX_PCS_BASE + 0x1218)
#define CSR_RX_PCS_PHY6_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x121c)
#define CSR_RX_PCS_PHY6_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1220)
#define CSR_RX_PCS_PHY6_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x1224)
#define CSR_RX_PCS_PHY6_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1228)
#define CSR_RX_PCS_PHY6_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x122c)
#define CSR_RX_PCS_PHY6_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1230)
#define CSR_RX_PCS_PHY6_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x1234)
#define CSR_RX_PCS_PHY6_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1238)
#define CSR_RX_PCS_PHY6_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x123c)
#define CSR_RX_PCS_PHY6_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1240)
#define CSR_RX_PCS_PHY6_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1244)
#define CSR_RX_PCS_PHY6_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1248)
#define CSR_RX_PCS_PHY6_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x124c)
#define CSR_RX_PCS_PHY6_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1250)
#define CSR_RX_PCS_PHY6_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1254)
#define CSR_RX_PCS_PHY6_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1258)
#define CSR_RX_PCS_PHY6_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x125c)
#define CSR_RX_PCS_PHY6_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x1260)
#define CSR_RX_PCS_PHY6_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x1264)
#define CSR_RX_PCS_PHY6_BER_CNT (CSR_RX_PCS_BASE + 0x1268)
#define CSR_RX_PCS_PHY6_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x126c)
#define CSR_RX_PCS_PHY6_E_BLK_CNT (CSR_RX_PCS_BASE + 0x1270)
#define CSR_RX_PCS_PHY6_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x1274)
#define CSR_RX_PCS_PHY6_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x1278)
#define CSR_RX_PCS_PHY6__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x1280)
#define CSR_RX_PCS_PHY6_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x1300)
#define CSR_RX_PCS_PHY6_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x1304)
#define CSR_RX_PCS_PHY6_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x1308)
#define CSR_RX_PCS_PHY6_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x130c)
#define CSR_RX_PCS_PHY6_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x1310)
#define CSR_RX_PCS_PHY7_CTRL_CFG (CSR_RX_PCS_BASE + 0x1400)
#define CSR_RX_PCS_PHY7_LINK_DOWN_FILTER_WIN (CSR_RX_PCS_BASE + 0x1404)
#define CSR_RX_PCS_PHY7_LINK_UP_FILTER_WIN (CSR_RX_PCS_BASE + 0x1408)
#define CSR_RX_PCS_PHY7_LINK_TIMEOUT_CFG (CSR_RX_PCS_BASE + 0x140c)
#define CSR_RX_PCS_PHY7_BER_CTRL_CFG (CSR_RX_PCS_BASE + 0x1410)
#define CSR_RX_PCS_PHY7_TEST_CONTROL (CSR_RX_PCS_BASE + 0x1414)
#define CSR_RX_PCS_PHY7_DBG_CONTROL (CSR_RX_PCS_BASE + 0x1418)
#define CSR_RX_PCS_PHY7_BIP_ERR_CFG (CSR_RX_PCS_BASE + 0x141c)
#define CSR_RX_PCS_PHY7_SD_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1420)
#define CSR_RX_PCS_PHY7_SD_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x1424)
#define CSR_RX_PCS_PHY7_SF_SET_WINDOW_NS (CSR_RX_PCS_BASE + 0x1428)
#define CSR_RX_PCS_PHY7_SF_CLR_WINDOW_NS (CSR_RX_PCS_BASE + 0x142c)
#define CSR_RX_PCS_PHY7_SD_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1430)
#define CSR_RX_PCS_PHY7_SD_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x1434)
#define CSR_RX_PCS_PHY7_SF_SET_WINDOW_B (CSR_RX_PCS_BASE + 0x1438)
#define CSR_RX_PCS_PHY7_SF_CLR_WINDOW_B (CSR_RX_PCS_BASE + 0x143c)
#define CSR_RX_PCS_PHY7_SD_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1440)
#define CSR_RX_PCS_PHY7_SD_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1444)
#define CSR_RX_PCS_PHY7_SF_SET_THRESHOLD_L (CSR_RX_PCS_BASE + 0x1448)
#define CSR_RX_PCS_PHY7_SF_CLR_THRESHOLD_L (CSR_RX_PCS_BASE + 0x144c)
#define CSR_RX_PCS_PHY7_SD_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1450)
#define CSR_RX_PCS_PHY7_SD_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1454)
#define CSR_RX_PCS_PHY7_SF_SET_THRESHOLD_M (CSR_RX_PCS_BASE + 0x1458)
#define CSR_RX_PCS_PHY7_SF_CLR_THRESHOLD_M (CSR_RX_PCS_BASE + 0x145c)
#define CSR_RX_PCS_PHY7_DBG_DEC_ERR_CTRL_CFG0 (CSR_RX_PCS_BASE + 0x1460)
#define CSR_RX_PCS_PHY7_DBG_DEC_ERR_CTRL_CFG1 (CSR_RX_PCS_BASE + 0x1464)
#define CSR_RX_PCS_PHY7_BER_CNT (CSR_RX_PCS_BASE + 0x1468)
#define CSR_RX_PCS_PHY7_ERR_BLOCK_CNT (CSR_RX_PCS_BASE + 0x146c)
#define CSR_RX_PCS_PHY7_E_BLK_CNT (CSR_RX_PCS_BASE + 0x1470)
#define CSR_RX_PCS_PHY7_DEC_ERR_BLK_CNT (CSR_RX_PCS_BASE + 0x1474)
#define CSR_RX_PCS_PHY7_TEST_ERR_CNT (CSR_RX_PCS_BASE + 0x1478)
#define CSR_RX_PCS_PHY7__LANE_BIP_ERR_CNT (CSR_RX_PCS_BASE + 0x1480)
#define CSR_RX_PCS_PHY7_LINK_TIMEOUT_STATUS (CSR_RX_PCS_BASE + 0x1500)
#define CSR_RX_PCS_PHY7_MUTIL_LANE_STATUS (CSR_RX_PCS_BASE + 0x1504)
#define CSR_RX_PCS_PHY7_DBG_64B66B_CURR_STATUS (CSR_RX_PCS_BASE + 0x1508)
#define CSR_RX_PCS_PHY7_DBG_CURR_STATUS (CSR_RX_PCS_BASE + 0x150c)
#define CSR_RX_PCS_PHY7_DBG_HIS_STATUS (CSR_RX_PCS_BASE + 0x1510)

#endif